Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by a tunneling layer. One of the two ferromagnetic layers, which is referred to as the fixed layer or pinned layer, has a magnetization that is fixed in a particular direction. The other ferromagnetic magnetic layer, which is referred to as the free layer, has a magnetization direction that can be altered to represent either a “1” when the free layer magnetization is anti-parallel to the fixed layer magnification or “0” when the free layer magnetization is parallel to the fixed layer magnitization or vice versa. One such device having a fixed layer, a tunneling layer, and a free layer is a magnetic tunnel junction (MTJ). An MTJ normally also includes top and bottom electrode and may be formed with or without an antiferromagnetic layer to pin the fixed layer. The electrical resistance of an MTJ depends on whether the free layer magnetization and fixed layer magnetization are parallel or anti-parallel with each other. A memory device such as Spin-Transfer Torque (STT) MRAM is built from an array of individually addressable MTJs.
To write data in STT MRAM, a write current with a specific direction of write “1” or “0”, which exceeds a critical switching current, is applied through an MTJ. The write current exceeding the critical switching current is sufficient to change the magnetization direction of the free layer. When the write current flows in a first direction, the MTJ can be placed into or remain in a first state, in which its free layer magnetization direction and fixed layer magnetization direction are aligned in a parallel orientation. When the write current flows in a second direction, opposite to the first direction, the MTJ can be placed into or remain in a second state, in which its free layer magnetization and fixed layer magnetization are in an anti-parallel orientation.
To read data in a conventional MRAM, a read current may flow through the MTJ via the same current path used to write data in the MTJ. If the magnetizations of the MTJ's free layer and fixed layer are oriented parallel to each other, the MTJ presents a resistance that is different than the resistance the MTJ would present if the magnetizations of the free layer and the fixed layer were in an anti-parallel orientation. In STT MRAM, two distinct states are defined be two different resistances of an MTJ in a bitcell of the MRAM. The two different resistances represent a logic “0” and a logic “1” value stored by the MTJ.
Magnetic tunnel junctions (MTJs) can be used to construct non-volatile flip-flop structures (NVFF). Sensing circuitry in non-volatile flip flop structures have included cross-coupled inverter configurations in which two magnetic tunnel junctions (MTJs) are embedded in the cross-coupled inverter. FIG. 1 shows sense amplifier circuitry 100 that has been proposed for sensing the state of MTJs in a flip flop circuit as described in Weisheng Zhao, Eric Belbaire, Claude Chappert, “Spin-MTJ based Non-Volatile Flip-Flop”, Proc. Of IEEE International Conference on Nanotechnology (IEEE-NANO), Hongkong, China, 2007. pp. 399-402, ISBN: 978-1-4244-0607-4, DOI: 10.1109/NANO.2007,4601218. Because this sense amplifier circuitry 100 is less precise than a standard, more complex MRAM sense amplifier, two complementary MTJs are used for each bit to increase robustness. A sense operation is performed by briefly turning on the NMOS transistor MN2 and then promptly turning it off. In FIG. 1, SE is the read control (sense enable) signal.
FIG. 2 shows a pre-charged sense amplifier (PCSA) 200 that has been proposed in Weisheng Zhao, Claude Chappert, Virgile Javerliac and Jean-Pierre Noiziére, “High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits”, IEEE Transaction on Magnetics, Vol. 45, October 2009, pp. 3784-3787. DOI: 10.1109/TMAG.2009.2024325. The pre-charge sense amplifier 200 includes two inverters (MP0, MN0 and MP1, MN1), two PMOS transistors (MP2, MP3) in parallel with MP0 and MP1, respectively, and one NMOS transistor MN2 connecting the circuit with ground (GND). The pre-charge sense amplifier 200 uses two operating phases depending on the control signal SE.
When SE is set to 0, the pre-charge sense amplifier pre-charges the polarization voltages (V0 and V1) of the two MTJs. There is no stationary current in the circuit because MN2 is closed. As SE is then set from 0 to 1, the pre-charged voltages begin to discharge. Because the two MTJs have different resistances, the discharge speed will be different for each branch. For example, if ferromagnetic layers of MTJ1 are anti-parallel and those of MTJ2 are parallel, the resistance of MTJ1 is greater than the resistance of MTJ2 and the discharge current through MTJ2 will be higher than the discharge current through MTJ1. During this discharge, a voltage Qm will be reduced faster than Qm bar. When Qm becomes less than the threshold switching voltage of the inverter amplifier composed of MP1 and MN1, Qm bar will be charged to the Vdd logic level, representing logical 1 and Qm will continue the discharge process down to 0.
The pre-charge sense amplifier circuitry shown in FIG. 2 was proposed to have very low power consumption because only current for charging or discharging capacitors should flow through the pre-charge sense amplifier circuitry. However, this structure actually includes a DC path from VDD to GND during the sensing operation, which allows a large sensing current to pass through the MTJs. This large sensing current can then cause read disturbance that may write unwanted data to the MTJs.